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kalipso
2022-12-18 15:37:26 +01:00
commit 514670e897
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372
cmake/stm32/common.cmake Normal file
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set(STM32_SUPPORTED_FAMILIES_LONG_NAME
STM32F0 STM32F1 STM32F2 STM32F3 STM32F4 STM32F7
STM32G0 STM32G4
STM32H7_M4 STM32H7_M7
STM32L0 STM32L1 STM32L4 STM32L5
STM32U5
STM32WB_M4 STM32WL_M4 STM32WL_M0PLUS
STM32MP1_M4 )
foreach(FAMILY ${STM32_SUPPORTED_FAMILIES_LONG_NAME})
# append short names (F0, F1, H7_M4, ...) to STM32_SUPPORTED_FAMILIES_SHORT_NAME
string(REGEX MATCH "^STM32([FGHLMUW]P?[0-9BL])_?(M0PLUS|M4|M7)?" FAMILY ${FAMILY})
list(APPEND STM32_SUPPORTED_FAMILIES_SHORT_NAME ${CMAKE_MATCH_1})
endforeach()
list(REMOVE_DUPLICATES STM32_SUPPORTED_FAMILIES_SHORT_NAME)
if(NOT STM32_TOOLCHAIN_PATH)
if(DEFINED ENV{STM32_TOOLCHAIN_PATH})
message(STATUS "Detected toolchain path STM32_TOOLCHAIN_PATH in environmental variables: ")
message(STATUS "$ENV{STM32_TOOLCHAIN_PATH}")
set(STM32_TOOLCHAIN_PATH $ENV{STM32_TOOLCHAIN_PATH})
else()
if(NOT CMAKE_C_COMPILER)
set(STM32_TOOLCHAIN_PATH "/usr")
message(STATUS "No STM32_TOOLCHAIN_PATH specified, using default: " ${STM32_TOOLCHAIN_PATH})
else()
# keep only directory of compiler
get_filename_component(STM32_TOOLCHAIN_PATH ${CMAKE_C_COMPILER} DIRECTORY)
# remove the last /bin directory
get_filename_component(STM32_TOOLCHAIN_PATH ${STM32_TOOLCHAIN_PATH} DIRECTORY)
endif()
endif()
file(TO_CMAKE_PATH "${STM32_TOOLCHAIN_PATH}" STM32_TOOLCHAIN_PATH)
endif()
if(NOT STM32_TARGET_TRIPLET)
set(STM32_TARGET_TRIPLET "arm-none-eabi")
message(STATUS "No STM32_TARGET_TRIPLET specified, using default: " ${STM32_TARGET_TRIPLET})
endif()
set(CMAKE_SYSTEM_NAME Generic)
set(CMAKE_SYSTEM_PROCESSOR arm)
set(TOOLCHAIN_SYSROOT "${STM32_TOOLCHAIN_PATH}/${STM32_TARGET_TRIPLET}")
set(TOOLCHAIN_BIN_PATH "${STM32_TOOLCHAIN_PATH}/bin")
set(TOOLCHAIN_INC_PATH "${STM32_TOOLCHAIN_PATH}/${STM32_TARGET_TRIPLET}/include")
set(TOOLCHAIN_LIB_PATH "${STM32_TOOLCHAIN_PATH}/${STM32_TARGET_TRIPLET}/lib")
find_program(CMAKE_OBJCOPY NAMES ${STM32_TARGET_TRIPLET}-objcopy HINTS ${TOOLCHAIN_BIN_PATH})
find_program(CMAKE_OBJDUMP NAMES ${STM32_TARGET_TRIPLET}-objdump HINTS ${TOOLCHAIN_BIN_PATH})
find_program(CMAKE_SIZE NAMES ${STM32_TARGET_TRIPLET}-size HINTS ${TOOLCHAIN_BIN_PATH})
find_program(CMAKE_DEBUGGER NAMES ${STM32_TARGET_TRIPLET}-gdb HINTS ${TOOLCHAIN_BIN_PATH})
find_program(CMAKE_CPPFILT NAMES ${STM32_TARGET_TRIPLET}-c++filt HINTS ${TOOLCHAIN_BIN_PATH})
function(stm32_print_size_of_target TARGET)
add_custom_target(${TARGET}_always_display_size
ALL COMMAND ${CMAKE_SIZE} ${TARGET}${CMAKE_EXECUTABLE_SUFFIX_C}
COMMENT "Target Sizes: "
DEPENDS ${TARGET}
)
endfunction()
function(stm32_generate_binary_file TARGET)
add_custom_command(
TARGET ${TARGET}
POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -O binary ${TARGET}${CMAKE_EXECUTABLE_SUFFIX_C} ${TARGET}.bin
BYPRODUCTS ${TARGET}.bin
COMMENT "Generating binary file ${CMAKE_PROJECT_NAME}.bin"
)
endfunction()
function(stm32_generate_srec_file TARGET)
add_custom_command(
TARGET ${TARGET}
POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -O srec ${TARGET}${CMAKE_EXECUTABLE_SUFFIX_C} ${TARGET}.srec
BYPRODUCTS ${TARGET}.srec
COMMENT "Generating srec file ${CMAKE_PROJECT_NAME}.srec"
)
endfunction()
function(stm32_generate_hex_file TARGET)
add_custom_command(
TARGET ${TARGET}
POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -O ihex ${TARGET}${CMAKE_EXECUTABLE_SUFFIX_C} ${TARGET}.hex
BYPRODUCTS ${TARGET}.hex
COMMENT "Generating hex file ${CMAKE_PROJECT_NAME}.hex"
)
endfunction()
# This function takes FAMILY (e.g. L4) and DEVICE (e.g. L496VG) to output TYPE (e.g. L496xx)
function(stm32_get_chip_type FAMILY DEVICE TYPE)
set(INDEX 0)
foreach(C_TYPE ${STM32_${FAMILY}_TYPES})
list(GET STM32_${FAMILY}_TYPE_MATCH ${INDEX} REGEXP)
if(${DEVICE} MATCHES ${REGEXP})
set(RESULT_TYPE ${C_TYPE})
endif()
math(EXPR INDEX "${INDEX}+1")
endforeach()
if(NOT RESULT_TYPE)
message(FATAL_ERROR "Invalid/unsupported device: ${DEVICE}")
endif()
set(${TYPE} ${RESULT_TYPE} PARENT_SCOPE)
endfunction()
function(stm32_get_chip_info CHIP)
set(ARG_OPTIONS "")
set(ARG_SINGLE FAMILY DEVICE TYPE)
set(ARG_MULTIPLE "")
cmake_parse_arguments(PARSE_ARGV 1 ARG "${ARG_OPTIONS}" "${ARG_SINGLE}" "${ARG_MULTIPLE}")
string(TOUPPER ${CHIP} CHIP)
string(REGEX MATCH "^STM32([FGHLMUW]P?[0-9BL])([0-9A-Z][0-9M][A-Z][0-9A-Z]).*$" CHIP ${CHIP})
if((NOT CMAKE_MATCH_1) OR (NOT CMAKE_MATCH_2))
message(FATAL_ERROR "Unknown chip ${CHIP}")
endif()
set(STM32_FAMILY ${CMAKE_MATCH_1})
set(STM32_DEVICE "${CMAKE_MATCH_1}${CMAKE_MATCH_2}")
if(NOT (${STM32_FAMILY} IN_LIST STM32_SUPPORTED_FAMILIES_SHORT_NAME))
message(FATAL_ERROR "Unsupported family ${STM32_FAMILY} for device ${CHIP}")
endif()
stm32_get_chip_type(${STM32_FAMILY} ${STM32_DEVICE} STM32_TYPE)
if(ARG_FAMILY)
set(${ARG_FAMILY} ${STM32_FAMILY} PARENT_SCOPE)
endif()
if(ARG_DEVICE)
set(${ARG_DEVICE} ${STM32_DEVICE} PARENT_SCOPE)
endif()
if(ARG_TYPE)
set(${ARG_TYPE} ${STM32_TYPE} PARENT_SCOPE)
endif()
endfunction()
function(stm32_get_cores CORES)
set(ARG_OPTIONS "")
set(ARG_SINGLE CHIP FAMILY DEVICE)
set(ARG_MULTIPLE "")
cmake_parse_arguments(PARSE_ARGV 1 ARG "${ARG_OPTIONS}" "${ARG_SINGLE}" "${ARG_MULTIPLE}")
if(ARG_CHIP)
# TODO: I don't get why stm32_get_chip_info is called in stm32_get_cores
stm32_get_chip_info(${ARG_CHIP} FAMILY ARG_FAMILY TYPE ARG_TYPE DEVICE ARG_DEVICE)
elseif(ARG_FAMILY AND ARG_DEVICE)
# TODO: I don't get why stm32_get_chip_type is called in stm32_get_cores
stm32_get_chip_type(${ARG_FAMILY} ${ARG_DEVICE} ARG_TYPE)
elseif(ARG_FAMILY)
if(${ARG_FAMILY} STREQUAL "H7")
set(${CORES} M7 M4 PARENT_SCOPE)
elseif(${ARG_FAMILY} STREQUAL "WB")
set(${CORES} M4 PARENT_SCOPE)
elseif(${ARG_FAMILY} STREQUAL "WL")
set(${CORES} M4 M0PLUS PARENT_SCOPE)
elseif(${ARG_FAMILY} STREQUAL "MP1")
set(${CORES} M4 PARENT_SCOPE)
else()
set(${CORES} "" PARENT_SCOPE)
endif()
return()
else()
message(FATAL_ERROR "Either CHIP or FAMILY or FAMILY/DEVICE should be specified for stm32_get_cores()")
endif()
# TODO following is the only part really used by FindCMSIS. Maybe a cleanup is needed
if(${ARG_FAMILY} STREQUAL "H7")
stm32h7_get_device_cores(${ARG_DEVICE} ${ARG_TYPE} CORE_LIST)
elseif(${ARG_FAMILY} STREQUAL "WB")
# note STM32WB have an M0 core but in current state of the art it runs ST stacks and is not needed/allowed to build for customer
set(CORE_LIST M4)
elseif(${ARG_FAMILY} STREQUAL "MP1")
set(CORE_LIST M4)
elseif(${ARG_FAMILY} STREQUAL "WL")
stm32wl_get_device_cores(${ARG_DEVICE} ${ARG_TYPE} CORE_LIST)
endif()
set(${CORES} "${CORE_LIST}" PARENT_SCOPE)
endfunction()
function(stm32_get_memory_info)
set(ARG_OPTIONS FLASH RAM CCRAM STACK HEAP RAM_SHARE)
set(ARG_SINGLE CHIP FAMILY DEVICE CORE SIZE ORIGIN)
set(ARG_MULTIPLE "")
cmake_parse_arguments(INFO "${ARG_OPTIONS}" "${ARG_SINGLE}" "${ARG_MULTIPLE}" ${ARGN})
if((NOT INFO_CHIP) AND ((NOT INFO_FAMILY) OR (NOT INFO_DEVICE)))
message(FATAL_ERROR "Either CHIP or FAMILY/DEVICE is required for stm32_get_memory_info()")
endif()
if(INFO_CHIP)
stm32_get_chip_info(${INFO_CHIP} FAMILY INFO_FAMILY TYPE INFO_TYPE DEVICE INFO_DEVICE)
else()
stm32_get_chip_type(${INFO_FAMILY} ${INFO_DEVICE} INFO_TYPE)
endif()
string(REGEX REPLACE "^[FGHLMUW]P?[0-9BL][0-9A-Z][0-9M].([3468ABCDEFGHIYZ])$" "\\1" SIZE_CODE ${INFO_DEVICE})
if(SIZE_CODE STREQUAL "3")
set(FLASH "8K")
elseif(SIZE_CODE STREQUAL "4")
set(FLASH "16K")
elseif(SIZE_CODE STREQUAL "6")
set(FLASH "32K")
elseif(SIZE_CODE STREQUAL "8")
set(FLASH "64K")
elseif(SIZE_CODE STREQUAL "B")
set(FLASH "128K")
elseif(SIZE_CODE STREQUAL "C")
set(FLASH "256K")
elseif(SIZE_CODE STREQUAL "D")
set(FLASH "384K")
elseif(SIZE_CODE STREQUAL "E")
set(FLASH "512K")
elseif(SIZE_CODE STREQUAL "F")
set(FLASH "768K")
elseif(SIZE_CODE STREQUAL "G")
set(FLASH "1024K")
elseif(SIZE_CODE STREQUAL "H")
set(FLASH "1536K")
elseif(SIZE_CODE STREQUAL "I")
set(FLASH "2048K")
elseif(SIZE_CODE STREQUAL "Y")
set(FLASH "640K")
elseif(SIZE_CODE STREQUAL "Z")
set(FLASH "192K")
else()
set(FLASH "16K")
message(WARNING "Unknow flash size for device ${DEVICE}. Set to ${FLASH}")
endif()
list(FIND STM32_${INFO_FAMILY}_TYPES ${INFO_TYPE} TYPE_INDEX)
list(GET STM32_${INFO_FAMILY}_RAM_SIZES ${TYPE_INDEX} RAM)
list(GET STM32_${INFO_FAMILY}_CCRAM_SIZES ${TYPE_INDEX} CCRAM)
list(GET STM32_${INFO_FAMILY}_RAM_SHARE_SIZES ${TYPE_INDEX} RAM_SHARE)
set(FLASH_ORIGIN 0x8000000)
set(RAM_ORIGIN 0x20000000)
set(CCRAM_ORIGIN 0x10000000)
set(RAM_SHARE_ORIGIN 0x20030000)
unset(TWO_FLASH_BANKS)
if(FAMILY STREQUAL "F1")
stm32f1_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} FLASH RAM)
elseif(FAMILY STREQUAL "L1")
stm32l1_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} FLASH RAM)
elseif(FAMILY STREQUAL "F2")
stm32f2_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} FLASH RAM)
elseif(FAMILY STREQUAL "F3")
stm32f3_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} FLASH RAM)
elseif(FAMILY STREQUAL "H7")
stm32h7_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} "${INFO_CORE}" RAM FLASH_ORIGIN RAM_ORIGIN TWO_FLASH_BANKS)
elseif(FAMILY STREQUAL "WL")
stm32wl_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} "${INFO_CORE}" RAM FLASH_ORIGIN RAM_ORIGIN TWO_FLASH_BANKS)
elseif(FAMILY STREQUAL "WB")
stm32wb_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} "${INFO_CORE}" RAM RAM_ORIGIN TWO_FLASH_BANKS)
elseif(FAMILY STREQUAL "MP1")
stm32mp1_get_memory_info(${INFO_DEVICE} ${INFO_TYPE} FLASH)
endif()
# when a device is dual core, each core uses half of total flash
if(TWO_FLASH_BANKS)
string(REGEX MATCH "([0-9]+)K" FLASH_KB ${FLASH})
math(EXPR FLASH_KB "${CMAKE_MATCH_1} / 2")
set(FLASH "${FLASH_KB}K")
endif()
if(INFO_FLASH)
set(SIZE ${FLASH})
set(ORIGIN ${FLASH_ORIGIN})
elseif(INFO_RAM)
set(SIZE ${RAM})
set(ORIGIN ${RAM_ORIGIN})
elseif(INFO_CCRAM)
set(SIZE ${CCRAM})
set(ORIGIN ${CCRAM_ORIGIN})
elseif(INFO_RAM_SHARE)
set(SIZE ${RAM_SHARE})
set(ORIGIN ${RAM_SHARE_ORIGIN})
elseif(INFO_STACK)
if (RAM STREQUAL "2K")
set(SIZE 0x200)
else()
set(SIZE 0x400)
endif()
set(ORIGIN ${RAM_ORIGIN}) #TODO: Real stack pointer?
elseif(INFO_HEAP)
if (RAM STREQUAL "2K")
set(SIZE 0x100)
else()
set(SIZE 0x200)
endif()
set(ORIGIN ${RAM_ORIGIN}) #TODO: Real heap pointer?
endif()
if(INFO_SIZE)
set(${INFO_SIZE} ${SIZE} PARENT_SCOPE)
endif()
if(INFO_ORIGIN)
set(${INFO_ORIGIN} ${ORIGIN} PARENT_SCOPE)
endif()
endfunction()
function(stm32_add_linker_script TARGET VISIBILITY SCRIPT)
get_filename_component(SCRIPT "${SCRIPT}" ABSOLUTE)
target_link_options(${TARGET} ${VISIBILITY} -T "${SCRIPT}")
get_target_property(TARGET_TYPE ${TARGET} TYPE)
if(TARGET_TYPE STREQUAL "INTERFACE_LIBRARY")
set(INTERFACE_PREFIX "INTERFACE_")
endif()
get_target_property(LINK_DEPENDS ${TARGET} ${INTERFACE_PREFIX}LINK_DEPENDS)
if(LINK_DEPENDS)
list(APPEND LINK_DEPENDS "${SCRIPT}")
else()
set(LINK_DEPENDS "${SCRIPT}")
endif()
set_target_properties(${TARGET} PROPERTIES ${INTERFACE_PREFIX}LINK_DEPENDS "${LINK_DEPENDS}")
endfunction()
if(NOT (TARGET STM32::NoSys))
add_library(STM32::NoSys INTERFACE IMPORTED)
target_compile_options(STM32::NoSys INTERFACE $<$<C_COMPILER_ID:GNU>:--specs=nosys.specs>)
target_link_options(STM32::NoSys INTERFACE $<$<C_COMPILER_ID:GNU>:--specs=nosys.specs>)
endif()
if(NOT (TARGET STM32::Nano))
add_library(STM32::Nano INTERFACE IMPORTED)
target_compile_options(STM32::Nano INTERFACE $<$<C_COMPILER_ID:GNU>:--specs=nano.specs>)
target_link_options(STM32::Nano INTERFACE $<$<C_COMPILER_ID:GNU>:--specs=nano.specs>)
endif()
if(NOT (TARGET STM32::Nano::FloatPrint))
add_library(STM32::Nano::FloatPrint INTERFACE IMPORTED)
target_link_options(STM32::Nano::FloatPrint INTERFACE
$<$<C_COMPILER_ID:GNU>:-Wl,--undefined,_printf_float>
)
endif()
if(NOT (TARGET STM32::Nano::FloatScan))
add_library(STM32::Nano::FloatScan INTERFACE IMPORTED)
target_link_options(STM32::Nano::FloatScan INTERFACE
$<$<C_COMPILER_ID:GNU>:-Wl,--undefined,_scanf_float>
)
endif()
include(stm32/utilities)
include(stm32/f0)
include(stm32/f1)
include(stm32/f2)
include(stm32/f3)
include(stm32/f4)
include(stm32/f7)
include(stm32/g0)
include(stm32/g4)
include(stm32/h7)
include(stm32/l0)
include(stm32/l1)
include(stm32/l4)
include(stm32/l5)
include(stm32/u5)
include(stm32/wb)
include(stm32/wl)
include(stm32/mp1)

1258
cmake/stm32/devices.cmake Normal file
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25
cmake/stm32/f0.cmake Normal file
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set(STM32_F0_TYPES
F030x6 F030x8 F031x6 F038xx F042x6 F048xx F051x8 F058xx
F070x6 F070xB F071xB F072xB F078xx F091xC F098xx F030xC
)
set(STM32_F0_TYPE_MATCH
"F030.[46]" "F030.8" "F031.[46]" "F038.." "F042.[46]" "F048.." "F051.[468]" "F058.."
"F070.6" "F070.B" "F071.[8B]" "F072.[8B]" "F078.." "F091.[BC]" "F098.." "F030.C"
)
set(STM32_F0_RAM_SIZES
4K 8K 4K 4K 6K 6K 8K 8K
6K 16K 16K 16K 16K 32K 32K 32K
)
set(STM32_F0_CCRAM_SIZES
0K 0K 0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 0K 0K 0K 0K
)
stm32_util_create_family_targets(F0)
target_compile_options(STM32::F0 INTERFACE
-mcpu=cortex-m0
)
target_link_options(STM32::F0 INTERFACE
-mcpu=cortex-m0
)

78
cmake/stm32/f1.cmake Normal file
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set(STM32_F1_TYPES
F100xB F100xE F101x6 F101xB F101xE F101xG F102x6 F102xB
F103x6 F103xB F103xE F103xG F105xC F107xC
)
set(STM32_F1_TYPE_MATCH
"F100.[468B]" "F100.[CDE]" "F101.[46]" "F101.[8B]" "F101.[CDE]" "F101.[FG]" "F102.[46]" "F102.[8B]"
"F103.[46]" "F103.[8B]" "F103.[CDE]" "F103.[FG]" "F105.[8BC]" "F107.[BC]"
)
set(STM32_F1_RAM_SIZES
0K 0K 0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 0K 0K
)
set(STM32_F1_CCRAM_SIZES
0K 0K 0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 0K 0K
)
stm32_util_create_family_targets(F1)
target_compile_options(STM32::F1 INTERFACE
-mcpu=cortex-m3
)
target_link_options(STM32::F1 INTERFACE
-mcpu=cortex-m3
)
function(stm32f1_get_memory_info DEVICE TYPE FLASH_SIZE RAM_SIZE)
string(REGEX REPLACE "F1[0-9][0-9].([468BCDEFGHI])" "\\1" SIZE_CODE ${DEVICE})
if((TYPE STREQUAL "F100xB") OR (TYPE STREQUAL "F100xE"))
if((SIZE_CODE STREQUAL "4") OR (SIZE_CODE STREQUAL "6"))
set(RAM "4K")
elseif((SIZE_CODE STREQUAL "8") OR (SIZE_CODE STREQUAL "B"))
set(RAM "8K")
elseif(SIZE_CODE STREQUAL "C")
set(RAM "24K")
elseif((SIZE_CODE STREQUAL "D") OR (SIZE_CODE STREQUAL "E"))
set(RAM "32K")
endif()
elseif((TYPE STREQUAL "F101x6") OR (TYPE STREQUAL "F101xB") OR
(TYPE STREQUAL "F101xE") OR (TYPE STREQUAL "F101xG") OR
(TYPE STREQUAL "F102x6") OR (TYPE STREQUAL "F102xB"))
if(SIZE_CODE STREQUAL "4")
set(RAM "4K")
elseif(SIZE_CODE STREQUAL "6")
set(RAM "6K")
elseif(SIZE_CODE STREQUAL "8")
set(RAM "10K")
elseif(SIZE_CODE STREQUAL "B")
set(RAM "16K")
elseif(SIZE_CODE STREQUAL "C")
set(RAM "32K")
elseif((SIZE_CODE STREQUAL "D") OR (SIZE_CODE STREQUAL "E"))
set(RAM "48K")
elseif((SIZE_CODE STREQUAL "F") OR (SIZE_CODE STREQUAL "G"))
set(RAM "80K")
endif()
elseif((TYPE STREQUAL "F103x6") OR (TYPE STREQUAL "F103xB") OR
(TYPE STREQUAL "F103xE") OR (TYPE STREQUAL "F103xG"))
if(SIZE_CODE STREQUAL "4")
set(RAM "6K")
elseif(SIZE_CODE STREQUAL "6")
set(RAM "10K")
elseif((SIZE_CODE STREQUAL "8") OR (SIZE_CODE STREQUAL "B"))
set(RAM "20K")
elseif(SIZE_CODE STREQUAL "C")
set(RAM "48K")
elseif((SIZE_CODE STREQUAL "D") OR (SIZE_CODE STREQUAL "E"))
set(RAM "64K")
elseif((SIZE_CODE STREQUAL "F") OR (SIZE_CODE STREQUAL "G"))
set(RAM "96K")
endif()
elseif((TYPE STREQUAL "F105xC") OR (TYPE STREQUAL "F107xC"))
set(RAM "64K")
endif()
set(${RAM_SIZE} ${RAM} PARENT_SCOPE)
endfunction()

39
cmake/stm32/f2.cmake Normal file
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set(STM32_F2_TYPES
F205xx F215xx F207xx F217xx
)
set(STM32_F2_TYPE_MATCH
"F205.." "F215.." "F207.." "F217.."
)
set(STM32_F2_RAM_SIZES
0K 128K 128K 128K
)
set(STM32_F2_CCRAM_SIZES
0K 0K 0K 0K
)
stm32_util_create_family_targets(F2)
target_compile_options(STM32::F2 INTERFACE
-mcpu=cortex-m3
)
target_link_options(STM32::F2 INTERFACE
-mcpu=cortex-m3
)
function(stm32f2_get_memory_info DEVICE TYPE FLASH_SIZE RAM_SIZE)
string(REGEX REPLACE "F2[0-9][0-9].([468BCDEFGHI])" "\\1" SIZE_CODE ${DEVICE})
if(TYPE STREQUAL "F205xx")
if(SIZE_CODE STREQUAL "B")
set(RAM "64K")
elseif(SIZE_CODE STREQUAL "C")
set(RAM "96K")
else()
set(RAM "128K")
endif()
endif()
if(RAM)
set(${RAM_SIZE} ${RAM} PARENT_SCOPE)
endif()
endfunction()

59
cmake/stm32/f3.cmake Normal file
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set(STM32_F3_TYPES
F301x8 F302x8 F302xC F302xE F303x8 F303xC
F303xE F318xx F328xx F334x8 F358xx F373xC
F378xx F398xx
)
set(STM32_F3_TYPE_MATCH
"301.[68]" "302.[68]" "302.[BC]" "302.[DE]" "303.[68]" "303.[BC]"
"303.[DE]" "318.." "328.." "334.[468]" "358.." "373.[8BC]"
"378.." "398.."
)
set(STM32_F3_RAM_SIZES
16K 16K 0K 64K 12K 0K
64K 16K 12K 12K 40K 0K
32K 64K
)
set(STM32_F3_CCRAM_SIZES
0K 0K 0K 0K 4K 8K
16K 0K 4K 4K 8K 0K
0K 16K
)
stm32_util_create_family_targets(F3)
target_compile_options(STM32::F3 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
)
target_link_options(STM32::F3 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
)
function(stm32f3_get_memory_info DEVICE TYPE FLASH_SIZE RAM_SIZE)
string(REGEX REPLACE "F3[0-9][0-9].([468BCDEFGHI])" "\\1" SIZE_CODE ${DEVICE})
if(TYPE STREQUAL "F302xC")
if(SIZE_CODE STREQUAL "C")
set(RAM "40K")
else()
set(RAM "32K")
endif()
elseif(TYPE STREQUAL "F303xC")
if(SIZE_CODE STREQUAL "C")
set(RAM "40K")
else()
set(RAM "32K")
endif()
elseif(TYPE STREQUAL "F373xC")
if(SIZE_CODE STREQUAL "B")
set(RAM "24K")
elseif(SIZE_CODE STREQUAL "C")
set(RAM "32K")
else()
set(RAM "16K")
endif()
endif()
if(RAM)
set(${RAM_SIZE} ${RAM} PARENT_SCOPE)
endif()
endfunction()

29
cmake/stm32/f4.cmake Normal file
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@@ -0,0 +1,29 @@
set(STM32_F4_TYPES
F401xC F401xE F405xx F407xx F410Cx F410Rx F410Tx F411xE
F412Cx F412Rx F412Vx F412Zx F413xx F415xx F417xx F423xx
F427xx F429xx F437xx F439xx F446xx F469xx F479xx
)
set(STM32_F4_TYPE_MATCH
"F401.[CB]" "F401.[ED]" "F405.." "F407.." "F410C." "F410R." "F410T." "F411.[CE]"
"F412C." "F412R." "F412V." "F412Z." "F413.." "F415.." "F417.." "F423.."
"F427.." "F429.." "F437.." "F439.." "F446.." "F469.." "F479.."
)
set(STM32_F4_RAM_SIZES
64K 96K 128K 128K 32K 32K 32K 128K
256K 256K 256K 256K 320K 128K 128K 320K
192K 192K 192K 192K 128K 320K 320K
)
set(STM32_F4_CCRAM_SIZES
0K 0K 64K 64K 0K 0K 0K 0K
0K 0K 0K 0K 0K 64K 64K 0K
64K 64K 64K 64K 0K 64K 64K
)
stm32_util_create_family_targets(F4)
target_compile_options(STM32::F4 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
)
target_link_options(STM32::F4 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
)

25
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set(STM32_F7_TYPES
F756xx F746xx F745xx F765xx F767xx F769xx F777xx F779xx
F722xx F723xx F732xx F733xx F730xx F750xx
)
set(STM32_F7_TYPE_MATCH
"F756.." "F746.." "F745.." "F765.." "F767.." "F769.." "F777.." "F77[89].."
"F722.." "F723.." "F732.." "F733.." "F730.." "F750.."
)
set(STM32_F7_RAM_SIZES
320K 320K 320K 512K 512K 512K 512K 512K
256K 256K 256K 256K 256K 320K
)
set(STM32_F7_CCRAM_SIZES
0K 0K 0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 0K 0K
)
stm32_util_create_family_targets(F7)
target_compile_options(STM32::F7 INTERFACE
-mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
)
target_link_options(STM32::F7 INTERFACE
-mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
)

25
cmake/stm32/g0.cmake Normal file
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set(STM32_G0_TYPES
G030xx G031xx G041xx G070xx G071xx G081xx
G0B1xx G0C1xx
)
set(STM32_G0_TYPE_MATCH
"G030.." "G031.." "G041.." "G070.." "G071.." "G081.."
"G0B1.." "G0C1.."
)
set(STM32_G0_RAM_SIZES
8K 8K 8K 36K 36K 36K
144k 144K
)
set(STM32_G0_CCRAM_SIZES
0K 0K 0K 0K 0K 0K
0K 0K
)
stm32_util_create_family_targets(G0)
target_compile_options(STM32::G0 INTERFACE
-mcpu=cortex-m0plus
)
target_link_options(STM32::G0 INTERFACE
-mcpu=cortex-m0plus
)

25
cmake/stm32/g4.cmake Normal file
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set(STM32_G4_TYPES
G431xx G441xx G471xx G473xx G483xx G474xx G484xx
G491xx G4A1xx
)
set(STM32_G4_TYPE_MATCH
"G431.." "G441.." "G471.." "G473.." "G483.." "G474.." "G484.."
"G491.." "G4A1.."
)
set(STM32_G4_RAM_SIZES
32K 32K 128K 128K 128K 128K 128K
112K 112K
)
set(STM32_G4_CCRAM_SIZES
0K 0K 0K 0K 0K 0K 0K
0K 0K
)
stm32_util_create_family_targets(G4)
target_compile_options(STM32::G4 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
)
target_link_options(STM32::G4 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
)

87
cmake/stm32/h7.cmake Normal file
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set(STM32_H7_TYPES
H723xx H725xx H730xx H730xxQ H733xx H735xx
H743xx H753xx H750xx H742xx H745xx H755xx H747xx H757xx
H7A3xx H7A3xxQ H7B3xx H7B3xxQ H7B0xx H7B0xxQ
)
set(STM32_H7_TYPE_MATCH
"H723.." "H725.." "H730.." "H730..Q" "H733.." "H735.."
"H743.." "H753.." "H750.." "H742.." "H745.." "H755.." "H747.." "H757.."
"H7A3.." "H7A3..Q" "H7B3.." "H7B3..Q" "H7B0.." "H7B0..Q"
)
set(STM32_H7_RAM_SIZES
128K 128K 128K 128K 128K 128K
128K 128K 128K 128K 128K 128K 128K 128K
128K 128K 128K 128K 128K 128K
)
set(STM32_H7_M4_RAM_SIZES
0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 288K 288K 288K 288K
0K 0K 0K 0K 0K 0K
)
set(STM32_H7_CCRAM_SIZES
0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 0K 0K
)
set(STM32_H7_DUAL_CORE
H745xx H755xx H747xx H757xx
)
stm32_util_create_family_targets(H7 M7)
target_compile_options(STM32::H7::M7 INTERFACE
-mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
)
target_link_options(STM32::H7::M7 INTERFACE
-mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
)
target_compile_definitions(STM32::H7::M7 INTERFACE
-DCORE_CM7
)
stm32_util_create_family_targets(H7 M4)
target_compile_options(STM32::H7::M4 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
)
target_link_options(STM32::H7::M4 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
)
target_compile_definitions(STM32::H7::M4 INTERFACE
-DCORE_CM4
)
function(stm32h7_get_memory_info DEVICE TYPE CORE RAM FLASH_ORIGIN RAM_ORIGIN TWO_FLASH_BANKS)
if(${TYPE} IN_LIST STM32_H7_DUAL_CORE)
set(${TWO_FLASH_BANKS} TRUE PARENT_SCOPE)
else()
set(${TWO_FLASH_BANKS} FALSE PARENT_SCOPE)
endif()
if(NOT CORE)
set(CORE "M7")
endif()
list(FIND STM32_H7_TYPES ${TYPE} TYPE_INDEX)
if(CORE STREQUAL "M7")
list(GET STM32_H7_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
set(${RAM} ${RAM_VALUE} PARENT_SCOPE)
set(${FLASH_ORIGIN} 0x8000000 PARENT_SCOPE)
set(${RAM_ORIGIN} 0x20000000 PARENT_SCOPE)
elseif((${TYPE} IN_LIST STM32_H7_DUAL_CORE) AND (CORE STREQUAL "M4"))
list(GET STM32_H7_M4_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
set(${RAM} ${RAM_VALUE} PARENT_SCOPE)
set(${FLASH_ORIGIN} 0x8100000 PARENT_SCOPE)
set(${RAM_ORIGIN} 0x10000000 PARENT_SCOPE)
else()
message(FATAL_ERROR "Unknown core ${CORE}")
endif()
endfunction()
function(stm32h7_get_device_cores DEVICE TYPE CORES)
if(${TYPE} IN_LIST STM32_H7_DUAL_CORE)
set(${CORES} M7 M4 PARENT_SCOPE)
else()
set(${CORES} M7 PARENT_SCOPE)
endif()
endfunction()

29
cmake/stm32/l0.cmake Normal file
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set(STM32_L0_TYPES
L010x4 L010x6 L010x8 L010xB L011xx L021xx L031xx L041xx
L051xx L052xx L053xx L061xx L062xx L063xx L071xx L072xx
L073xx L081xx L082xx L083xx
)
set(STM32_L0_TYPE_MATCH
"L010.4" "L010.6" "L010.8" "L010.B" "L011.." "L021.." "L031.." "L041.."
"L051.." "L052.." "L053.." "L061.." "L062.." "L063.." "L071.." "L072.."
"L073.." "L081.." "L082.." "L083.."
)
set(STM32_L0_RAM_SIZES
2K 8K 8K 20K 2K 2K 8K 8K
8K 8K 8K 8K 8K 8K 20K 20K
20K 20K 20K 20K
)
set(STM32_L0_CCRAM_SIZES
0K 0K 0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 0K 0K 0K 0K
0K 0K 0K 0K
)
stm32_util_create_family_targets(L0)
target_compile_options(STM32::L0 INTERFACE
-mcpu=cortex-m0plus
)
target_link_options(STM32::L0 INTERFACE
-mcpu=cortex-m0plus
)

73
cmake/stm32/l1.cmake Normal file
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set(STM32_L1_TYPES
L100xB L100xBA L100xC L151xB L151xBA L151xC L151xCA L151xD
L151xDX L151xE L152xB L152xBA L152xC L152xCA L152xD L152xDX
L152xE L162xC L162xCA L162xD L162xDX L162xE
)
set(STM32_L1_TYPE_MATCH
"L100.[68B]" "L100.[68B]A" "L100.C" "L151.[68B]" "L151.[68B]A" "L151.C" "L151.CA" "L151.D"
"L151.DX" "L151.E" "L152.[68B]" "L152.[68B]A" "L152.C" "L152.CA" "L152.D" "L152.DX"
"L152.E" "L162.C" "L162.CA" "L162.D" "L162.DX" "L162.E"
)
set(STM32_L1_RAM_SIZES
0K 0K 16K 0K 0K 32K 32K 48K
80K 80K 0K 0K 32K 32K 48K 80K
80K 32K 32K 48K 80K 80K
)
set(STM32_L1_CCRAM_SIZES
0K 0K 0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 0K 0K
)
stm32_util_create_family_targets(L1)
target_compile_options(STM32::L1 INTERFACE
-mcpu=cortex-m3
)
target_link_options(STM32::L1 INTERFACE
-mcpu=cortex-m3
)
function(stm32l1_get_memory_info DEVICE TYPE FLASH_SIZE RAM_SIZE)
string(REGEX REPLACE "L1[0-9][0-9].([68BCDE])" "\\1" SIZE_CODE ${DEVICE})
unset(RAM)
if((TYPE STREQUAL "L100xB"))
if(SIZE_CODE STREQUAL "6")
set(RAM "4K")
elseif(SIZE_CODE STREQUAL "8")
set(RAM "8K")
elseif(SIZE_CODE STREQUAL "B")
set(RAM "10K")
endif()
elseif((TYPE STREQUAL "L100xBA"))
if(SIZE_CODE STREQUAL "6")
set(RAM "4K")
elseif(SIZE_CODE STREQUAL "8")
set(RAM "8K")
elseif(SIZE_CODE STREQUAL "B")
set(RAM "16K")
endif()
elseif((TYPE STREQUAL "L151xB") OR (TYPE STREQUAL "L152xB"))
if(SIZE_CODE STREQUAL "6")
set(RAM "10K")
elseif(SIZE_CODE STREQUAL "8")
set(RAM "10K")
elseif(SIZE_CODE STREQUAL "B")
set(RAM "16K")
endif()
elseif((TYPE STREQUAL "L151xBA") OR (TYPE STREQUAL "L152xBA"))
if(SIZE_CODE STREQUAL "6")
set(RAM "16K")
elseif(SIZE_CODE STREQUAL "8")
set(RAM "32K")
elseif(SIZE_CODE STREQUAL "B")
set(RAM "32K")
endif()
endif()
if(RAM)
set(${RAM_SIZE} ${RAM} PARENT_SCOPE)
endif()
endfunction()

40
cmake/stm32/l4.cmake Normal file
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set(STM32_L4_TYPES
L412xx L422xx L431xx L432xx L433xx L442xx
L443xx L451xx L452xx L462xx L471xx L475xx
L476xx L485xx L486xx L496xx L4A6xx L4P5xx
L4Q5xx L4R5xx L4R7xx L4R9xx L4S5xx L4S7xx
L4S9xx
)
set(STM32_L4_TYPE_MATCH
"L412.." "L422.." "L431.." "L432.." "L433.." "L442.."
"L443.." "L451.." "L452.." "L462.." "L471.." "L475.."
"L476.." "L485.." "L486.." "L496.." "L4A6.." "L4P5.."
"L4Q5.." "L4R5.." "L4R7.." "L4R9.." "L4S5.." "L4S7.."
"L4S9.."
)
set(STM32_L4_RAM_SIZES
40K 40K 64K 64K 64K 64K
64K 160K 160K 160K 96K 96K
96K 96K 96K 320K 320K 320K
320K 640K 640K 640K 640K 640K
640K
)
# on devices where CCRAM is remapped to be contiguous with RAM it is included into RAM section
# If you want to have dedicated section then you will need to use custom linker script
set(STM32_L4_CCRAM_SIZES
0K 0K 0K 0K 0K 0K
0K 0K 0K 0K 32K 32K
32K 32K 32K 0K 0K 0K
0K 0K 0K 0K 0K 0K
0K
)
stm32_util_create_family_targets(L4)
target_compile_options(STM32::L4 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
)
target_link_options(STM32::L4 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
)

22
cmake/stm32/l5.cmake Normal file
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set(STM32_L5_TYPES
L552xx L562xx
)
set(STM32_L5_TYPE_MATCH
"L552.." "L562.."
)
set(STM32_L5_RAM_SIZES
256K 256K
)
set(STM32_L5_CCRAM_SIZES
0K 0K
)
stm32_util_create_family_targets(L5)
target_compile_options(STM32::L5 INTERFACE
-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
)
target_link_options(STM32::L5 INTERFACE
-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
)

158
cmake/stm32/linker_ld.cmake Normal file
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if((NOT CCRAM_SIZE) OR (CCRAM_SIZE STREQUAL "0K"))
set(CCRAM_DEFINITION "")
set(CCRAM_SECTION "")
else()
set(CCRAM_DEFINITION " CCMRAM (rw) : ORIGIN = ${CCRAM_ORIGIN}, LENGTH = ${CCRAM_SIZE}\n")
set(CCRAM_SECTION "
_siccmram = LOADADDR(.ccmram);\n\
.ccmram :\n\
{\n\
. = ALIGN(4);\n\
_sccmram = .;\n\
*(.ccmram)\n\
*(.ccmram*)\n\
. = ALIGN(4);\n\
_eccmram = .;\n\
} >CCMRAM AT> FLASH\n\
")
endif()
if((NOT RAM_SHARE_SIZE) OR (RAM_SHARE_SIZE STREQUAL "0K"))
set(RAM_SHARE_DEFINITION "")
set(RAM_SHARE_SECTION "")
else()
set(RAM_SHARE_DEFINITION " RAM_SHARED (rw) : ORIGIN = ${RAM_SHARE_ORIGIN}, LENGTH = ${RAM_SHARE_SIZE}\n")
set(RAM_SHARE_SECTION "
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED\n\
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED\n\
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED\n\
")
endif()
set(SCRIPT_TEXT
"ENTRY(Reset_Handler)\n\
\n\
_estack = ${RAM_ORIGIN} + ${RAM_SIZE};\n\
_Min_Heap_Size = ${HEAP_SIZE};\n\
_Min_Stack_Size = ${STACK_SIZE};\n\
\n\
MEMORY\n\
{\n\
FLASH (rx) : ORIGIN = ${FLASH_ORIGIN}, LENGTH = ${FLASH_SIZE}\n\
RAM (xrw) : ORIGIN = ${RAM_ORIGIN}, LENGTH = ${RAM_SIZE}\n\
${CCRAM_DEFINITION}\n\
${RAM_SHARE_DEFINITION}\n\
}\n\
\n\
SECTIONS\n\
{\n\
.isr_vector :\n\
{\n\
. = ALIGN(4);\n\
KEEP(*(.isr_vector))\n\
. = ALIGN(4);\n\
} >FLASH\n\
\n\
.text :\n\
{\n\
. = ALIGN(4);\n\
*(.text)\n\
*(.text*)\n\
*(.glue_7)\n\
*(.glue_7t)\n\
*(.eh_frame)\n\
\n\
KEEP (*(.init))\n\
KEEP (*(.fini))\n\
\n\
. = ALIGN(4);\n\
_etext = .;\n\
} >FLASH\n\
\n\
.rodata :\n\
{\n\
. = ALIGN(4);\n\
*(.rodata)\n\
*(.rodata*)\n\
. = ALIGN(4);\n\
} >FLASH\n\
\n\
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n\
.ARM : {\n\
__exidx_start = .;\n\
*(.ARM.exidx*)\n\
__exidx_end = .;\n\
} >FLASH\n\
\n\
.preinit_array :\n\
{\n\
PROVIDE_HIDDEN (__preinit_array_start = .);\n\
KEEP (*(.preinit_array*))\n\
PROVIDE_HIDDEN (__preinit_array_end = .);\n\
} >FLASH\n\
.init_array :\n\
{\n\
PROVIDE_HIDDEN (__init_array_start = .);\n\
KEEP (*(SORT(.init_array.*)))\n\
KEEP (*(.init_array*))\n\
PROVIDE_HIDDEN (__init_array_end = .);\n\
} >FLASH\n\
.fini_array :\n\
{\n\
PROVIDE_HIDDEN (__fini_array_start = .);\n\
KEEP (*(SORT(.fini_array.*)))\n\
KEEP (*(.fini_array*))\n\
PROVIDE_HIDDEN (__fini_array_end = .);\n\
} >FLASH\n\
\n\
_sidata = LOADADDR(.data);\n\
\n\
.data : \n\
{\n\
. = ALIGN(4);\n\
_sdata = .; \n\
*(.data)\n\
*(.data*)\n\
\n\
. = ALIGN(4);\n\
_edata = .;\n\
} >RAM AT> FLASH\n\
${CCRAM_SECTION}\n\
. = ALIGN(4);\n\
.bss :\n\
{\n\
_sbss = .;\n\
__bss_start__ = _sbss;\n\
*(.bss)\n\
*(.bss*)\n\
*(COMMON)\n\
\n\
. = ALIGN(4);\n\
_ebss = .;\n\
__bss_end__ = _ebss;\n\
} >RAM\n\
\n\
._user_heap_stack :\n\
{\n\
. = ALIGN(8);\n\
PROVIDE ( end = . );\n\
PROVIDE ( _end = . );\n\
. = . + _Min_Heap_Size;\n\
. = . + _Min_Stack_Size;\n\
. = ALIGN(8);\n\
} >RAM\n\
\n\
/DISCARD/ :\n\
{\n\
libc.a ( * )\n\
libm.a ( * )\n\
libgcc.a ( * )\n\
}\n\
\n\
.ARM.attributes 0 : { *(.ARM.attributes) }\n\
${RAM_SHARE_SECTION}\n\
}"
)
file(WRITE "${LINKER_SCRIPT}" "${SCRIPT_TEXT}")

31
cmake/stm32/mp1.cmake Normal file
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set(STM32_MP1_TYPES
MP151Axx MP151Cxx
MP153Axx MP153Cxx
MP157Axx MP157Cxx)
set(STM32_MP1_TYPE_MATCH
"MP151[AD](A.?)?" "MP151[CF](A.?)?"
"MP153[AD](A.?)?" "MP153[CF](A.?)?"
"MP157[AD](A.?)?" "MP157[CF](A.?)?")
set(STM32_MP1_RAM_SIZES
384K 384K
384K 384K
384K 384K)
set(STM32_MP1_CCRAM_SIZES
0K 0K
0K 0K
0K 0K)
stm32_util_create_family_targets(MP1 M4)
target_compile_options(STM32::MP1::M4 INTERFACE -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard)
target_link_options(STM32::MP1::M4 INTERFACE -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard)
target_compile_definitions(STM32::MP1::M4 INTERFACE CORE_CM4)
function(stm32mp1_get_memory_info DEVICE TYPE FLASH_SIZE)
if(FLASH_SIZE)
set(${FLASH_SIZE} "0KB" PARENT_SCOPE)
endif()
endfunction()

19
cmake/stm32/u5.cmake Normal file
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set(STM32_U5_TYPES
U575xx U585xx
)
set(STM32_U5_TYPE_MATCH
"U575.." "U585.."
)
set(STM32_U5_RAM_SIZES
768K 768K
)
stm32_util_create_family_targets(U5)
target_compile_options(STM32::U5 INTERFACE
-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
)
target_link_options(STM32::U5 INTERFACE
-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
)

161
cmake/stm32/utilities.cmake Normal file
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function(stm32_util_create_family_targets FAMILY)
set(CORES ${ARGN})
list(LENGTH CORES NUM_CORES)
if(${NUM_CORES} EQUAL 0)
set(CORE "")
set(CORE_C "")
elseif(${NUM_CORES} EQUAL 1)
set(CORE "_${CORES}")
set(CORE_C "::${CORES}")
else()
message(FATAL_ERROR "Expected at most one core for family ${FAMILY}: ${CORES}")
endif()
if(NOT (TARGET STM32::${FAMILY}${CORE_C}))
add_library(STM32::${FAMILY}${CORE_C} INTERFACE IMPORTED)
# Set compiler flags for target
# -Wall: all warnings activated
# -ffunction-sections -fdata-sections: remove unused code
target_compile_options(STM32::${FAMILY}${CORE_C} INTERFACE
--sysroot="${TOOLCHAIN_SYSROOT}"
-mthumb -Wall -ffunction-sections -fdata-sections
)
# Set linker flags
# -mthumb: Generate thumb code
# -Wl,--gc-sections: Remove unused code
target_link_options(STM32::${FAMILY}${CORE_C} INTERFACE
--sysroot="${TOOLCHAIN_SYSROOT}"
-mthumb -Wl,--gc-sections
)
target_compile_definitions(STM32::${FAMILY}${CORE_C} INTERFACE
STM32${FAMILY}
)
endif()
foreach(TYPE ${STM32_${FAMILY}_TYPES})
if(NOT (TARGET STM32::${TYPE}${CORE_C}))
add_library(STM32::${TYPE}${CORE_C} INTERFACE IMPORTED)
target_link_libraries(STM32::${TYPE}${CORE_C} INTERFACE STM32::${FAMILY}${CORE_C})
target_compile_definitions(STM32::${TYPE}${CORE_C} INTERFACE
STM32${TYPE}
)
endif()
endforeach()
endfunction()
include(FetchContent)
# A CMSIS or HAL driver can specify 'cube' as version number to indicate that the driver is taken from the Cube repository
set(STM32_FETCH_FAMILIES F0 F1 F2 F3 F4 F7 G0 G4 H7 L0 L1 L4 L5 MP1 U5 WB WL )
set(STM32_FETCH_CUBE_VERSIONS v1.11.2 v1.8.4 v1.9.3 v1.11.2 v1.26.1 v1.16.1 v1.4.1 v1.4.0 v1.9.0 v1.12.0 v1.10.3 v1.17.0 v1.4.0 1.5.0 v1.0.0 v1.12.0 v1.1.0)
set(STM32_FETCH_CMSIS_VERSIONS v2.3.5 v4.3.3 v2.2.5 v2.3.5 v2.6.6 v1.2.6 v1.4.0 v1.2.1 v1.10.0 v1.9.1 v2.3.2 v1.7.1 v1.0.4 cube v1.0.0 v1.9.0 v1.1.0)
set(STM32_FETCH_HAL_VERSIONS v1.7.5 v1.1.8 v1.2.7 v1.5.5 v1.7.12 v1.2.9 v1.4.1 v1.2.1 v1.10.0 v1.10.4 v1.4.4 v1.13.0 v1.0.4 cube v1.0.0 v1.9.0 v1.1.0)
FetchContent_Declare(
STM32-CMSIS
GIT_REPOSITORY https://github.com/STMicroelectronics/cmsis_core/
GIT_TAG v5.6.0
GIT_PROGRESS TRUE
)
set(IDX 0)
foreach(FAMILY ${STM32_FETCH_FAMILIES})
string(TOLOWER ${FAMILY} FAMILY_L)
list(GET STM32_FETCH_CUBE_VERSIONS ${IDX} CUBE_VERSION)
list(GET STM32_FETCH_CMSIS_VERSIONS ${IDX} CMSIS_VERSION)
list(GET STM32_FETCH_HAL_VERSIONS ${IDX} HAL_VERSION)
FetchContent_Declare(
STM32Cube${FAMILY}
GIT_REPOSITORY https://github.com/STMicroelectronics/STM32Cube${FAMILY}/
GIT_TAG ${CUBE_VERSION}
GIT_PROGRESS TRUE
)
if(CMSIS_VERSION STREQUAL cube)
set(STM32_USE_CMSIS_FROM_CUBE_${FAMILY} ON)
else()
FetchContent_Declare(
STM32-CMSIS-${FAMILY}
GIT_REPOSITORY https://github.com/STMicroelectronics/cmsis_device_${FAMILY_L}/
GIT_TAG ${CMSIS_VERSION}
GIT_PROGRESS TRUE
)
endif()
if(HAL_VERSION STREQUAL cube)
set(STM32_USE_HAL_FROM_CUBE_${FAMILY} ON)
else()
FetchContent_Declare(
STM32-HAL-${FAMILY}
GIT_REPOSITORY https://github.com/STMicroelectronics/stm32${FAMILY_L}xx_hal_driver/
GIT_TAG ${HAL_VERSION}
GIT_PROGRESS TRUE
)
endif()
math(EXPR IDX "${IDX} + 1")
endforeach()
function(stm32_fetch_cube)
foreach(FAMILY ${ARGV})
set(CUBE_NAME STM32Cube${FAMILY})
string(TOLOWER ${CUBE_NAME} CUBE_NAME_L)
if(STM32_CUBE_${FAMILY}_PATH)
message(VERBOSE "STM32_CUBE_${FAMILY}_PATH specified, skipping fetch for ${CUBE_NAME}")
continue()
endif()
FetchContent_MakeAvailable(${CUBE_NAME})
set(STM32_CUBE_${FAMILY}_PATH ${${CUBE_NAME_L}_SOURCE_DIR} PARENT_SCOPE)
endforeach()
endfunction()
function(stm32_fetch_cmsis)
if(NOT STM32_CMSIS_PATH)
FetchContent_MakeAvailable(STM32-CMSIS)
set(STM32_CMSIS_PATH ${stm32-cmsis_SOURCE_DIR} PARENT_SCOPE)
else()
message(INFO "STM32_CMSIS_PATH specified, skipping fetch for STM32-CMSIS")
endif()
foreach(FAMILY ${ARGV})
if(STM32_USE_CMSIS_FROM_CUBE_${FAMILY})
stm32_fetch_cube(${FAMILY})
message(STATUS "Cube fetched for ${FAMILY} at ${STM32_CUBE_${FAMILY}_PATH}")
set(STM32_CMSIS_${FAMILY}_PATH ${STM32_CUBE_${FAMILY}_PATH}/Drivers/CMSIS/Device/ST/STM32${FAMILY}xx PARENT_SCOPE)
else()
set(CMSIS_NAME STM32-CMSIS-${FAMILY})
string(TOLOWER ${CMSIS_NAME} CMSIS_NAME_L)
if(STM32_CMSIS_${FAMILY}_PATH)
message(INFO "STM32_CMSIS_${FAMILY}_PATH specified, skipping fetch for ${CMSIS_NAME}")
continue()
endif()
FetchContent_MakeAvailable(${CMSIS_NAME})
set(STM32_CMSIS_${FAMILY}_PATH ${${CMSIS_NAME_L}_SOURCE_DIR} PARENT_SCOPE)
endif()
endforeach()
endfunction()
function(stm32_fetch_hal)
foreach(FAMILY ${ARGV})
if(STM32_USE_HAL_FROM_CUBE_${FAMILY})
stm32_fetch_cube(${FAMILY})
message(STATUS "Cube fetched for ${FAMILY} at ${STM32_CUBE_${FAMILY}_PATH}")
set(STM32_HAL_${FAMILY}_PATH ${STM32_CUBE_${FAMILY}_PATH}/Drivers/STM32${FAMILY}xx_HAL_Driver PARENT_SCOPE)
else()
set(HAL_NAME STM32-HAL-${FAMILY})
string(TOLOWER ${HAL_NAME} HAL_NAME_L)
if(STM32_HAL_${FAMILY}_PATH)
message(INFO "STM32_HAL_${FAMILY}_PATH specified, skipping fetch for ${HAL_NAME}")
continue()
endif()
FetchContent_MakeAvailable(${HAL_NAME})
set(STM32_HAL_${FAMILY}_PATH ${${HAL_NAME_L}_SOURCE_DIR} PARENT_SCOPE)
endif()
endforeach()
endfunction()

38
cmake/stm32/wb.cmake Normal file
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set(STM32_WB_TYPES
WB55xx WB55xx WB35xx WB15xx WB50xx WB30xx WB10xx WB5Mxx
)
set(STM32_WB_TYPE_MATCH
"WB55.C" "WB55.[EGY]" "WB35.." "WB15.." "WB50.." "WB30.." "WB10.." "WB5M.."
)
# this is not full RAM of the chip but only the part allocated to M4 core (SRAM1 in datasheet)
set(STM32_WB_RAM_SIZES
64K 192K 32K 12K 64K 32K 12K 192K
)
# WB series need special area for SRAM2 shared with core M0PLUS
set(STM32_WB_RAM_SHARE_SIZES
10K 10K 10K 10K 10K 10K 10K 10K
)
set(STM32_WB_CCRAM_SIZES
0K 0K 0K 0K 0K 0K 0K 0K
)
stm32_util_create_family_targets(WB M4)
target_compile_options(STM32::WB::M4 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
)
target_link_options(STM32::WB::M4 INTERFACE
-mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
)
function(stm32wb_get_memory_info DEVICE TYPE CORE RAM RAM_ORIGIN TWO_FLASH_BANKS)
set(${TWO_FLASH_BANKS} TRUE PARENT_SCOPE)
list(FIND STM32_WB_TYPES ${TYPE} TYPE_INDEX)
list(GET STM32_WB_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
set(${RAM} "${RAM_VALUE}-4" PARENT_SCOPE)
set(${RAM_ORIGIN} 0x20000004 PARENT_SCOPE)
endfunction()

77
cmake/stm32/wl.cmake Normal file
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set(STM32_WL_TYPES
WL54xx WL55xx WLE4xx WLE5xx WLE4xx WLE5xx WLE4xx WLE5xx
)
set(STM32_WL_TYPE_MATCH
"WL54.." "WL55.." "WLE4.8" "WLE5.8" "WLE4.B" "WLE5.B" "WLE4.C" "WLE5.C"
)
# this is RAM size allocated to M4 core
# Note devices with 20 and 48K RAM can use only half of available RAM because
# there are 2 split sections of RAM and our default linker script only manages
# one section.
set(STM32_WL_RAM_SIZES
32K 32K 10K 10K 24K 24K 64K 64K
)
# this is RAM size allocated to M0PLUS core
set(STM32_WL_M0PLUS_RAM_SIZES
32K 32K 0K 0K 0K 0K 0K 0K
)
set(STM32_WL_CCRAM_SIZES
0K 0K 0K 0K 0K 0K 0K 0K
)
set(STM32_WL_DUAL_CORE
WL54xx WL55xx
)
stm32_util_create_family_targets(WL M4)
target_compile_options(STM32::WL::M4 INTERFACE
-mcpu=cortex-m4 -mfloat-abi=soft
)
target_link_options(STM32::WL::M4 INTERFACE
-mcpu=cortex-m4 -mfloat-abi=soft
)
stm32_util_create_family_targets(WL M0PLUS)
target_compile_options(STM32::WL::M0PLUS INTERFACE
-mcpu=cortex-m0plus -mfloat-abi=soft
)
target_link_options(STM32::WL::M0PLUS INTERFACE
-mcpu=cortex-m0plus -mfloat-abi=soft
)
function(stm32wl_get_memory_info DEVICE TYPE CORE RAM FLASH_ORIGIN RAM_ORIGIN TWO_FLASH_BANKS)
if(${TYPE} IN_LIST STM32_WL_DUAL_CORE)
set(${TWO_FLASH_BANKS} TRUE PARENT_SCOPE)
else()
set(${TWO_FLASH_BANKS} FALSE PARENT_SCOPE)
endif()
list(FIND STM32_WL_TYPES ${TYPE} TYPE_INDEX)
if(CORE STREQUAL "M4")
list(GET STM32_WL_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
set(${RAM} ${RAM_VALUE} PARENT_SCOPE)
set(${FLASH_ORIGIN} 0x8000000 PARENT_SCOPE)
set(${RAM_ORIGIN} 0x20000000 PARENT_SCOPE)
elseif((${TYPE} IN_LIST STM32_WL_DUAL_CORE) AND (CORE STREQUAL "M0PLUS"))
list(GET STM32_WL_M0PLUS_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
set(${RAM} ${RAM_VALUE} PARENT_SCOPE)
set(${FLASH_ORIGIN} 0x8020000 PARENT_SCOPE)
set(${RAM_ORIGIN} 0x20008000 PARENT_SCOPE)
else()
message(FATAL_ERROR "Unknown core ${CORE}")
endif()
endfunction()
function(stm32wl_get_device_cores DEVICE TYPE CORES)
if(${TYPE} IN_LIST STM32_WL_DUAL_CORE)
set(${CORES} M4 M0PLUS PARENT_SCOPE)
else()
set(${CORES} M4 PARENT_SCOPE)
endif()
endfunction()