39 lines
1.1 KiB
CMake
39 lines
1.1 KiB
CMake
set(STM32_WB_TYPES
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WB55xx WB55xx WB35xx WB15xx WB50xx WB30xx WB10xx WB5Mxx
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)
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set(STM32_WB_TYPE_MATCH
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"WB55.C" "WB55.[EGY]" "WB35.." "WB15.." "WB50.." "WB30.." "WB10.." "WB5M.."
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)
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# this is not full RAM of the chip but only the part allocated to M4 core (SRAM1 in datasheet)
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set(STM32_WB_RAM_SIZES
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64K 192K 32K 12K 64K 32K 12K 192K
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)
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# WB series need special area for SRAM2 shared with core M0PLUS
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set(STM32_WB_RAM_SHARE_SIZES
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10K 10K 10K 10K 10K 10K 10K 10K
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)
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set(STM32_WB_CCRAM_SIZES
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0K 0K 0K 0K 0K 0K 0K 0K
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)
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stm32_util_create_family_targets(WB M4)
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target_compile_options(STM32::WB::M4 INTERFACE
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-mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
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)
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target_link_options(STM32::WB::M4 INTERFACE
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-mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard
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)
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function(stm32wb_get_memory_info DEVICE TYPE CORE RAM RAM_ORIGIN TWO_FLASH_BANKS)
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set(${TWO_FLASH_BANKS} TRUE PARENT_SCOPE)
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list(FIND STM32_WB_TYPES ${TYPE} TYPE_INDEX)
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list(GET STM32_WB_RAM_SIZES ${TYPE_INDEX} RAM_VALUE)
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set(${RAM} "${RAM_VALUE}-4" PARENT_SCOPE)
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set(${RAM_ORIGIN} 0x20000004 PARENT_SCOPE)
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endfunction()
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