348 lines
15 KiB
C++
348 lines
15 KiB
C++
/*==============================================================================================================
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* To use this library a buffer called LoRa_buff has been created
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* and we'll have to configure the parameters for LoRa in the RF95_Init()
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1. include the declaration "extern uint8_t LoRa_buff[RH_RF95_FIFO_SIZE];" in the main.c.
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2. Follow these steps for the sending/reception of data:
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-----------Send Mode-------------
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RF95_Init();
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strcpy(LoRa_buff, "Test to send"); //It is necessary to use the buffer LoRa_buff and the function strcpy to
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//copy the data to the buffer, if not the program will send nothing.
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RF95_send(LoRa_buff);
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----------------------------------
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-----------Reception Mode-------------
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RF95_Init();
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RF95_setModeRx_Continuous();
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RF95_receive(LoRa_buff);
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----------------------------------
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==============================================================================================================*/
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#ifndef _LORA_RF95_
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#define _LORA_RF95_
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//#include "main.h"
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#include "spi.hpp"
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//#include "stm32l4xx_hal_def.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <string.h>
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//#include "Useful_Functions.h"
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//Modifiers for read and send
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#define W 0x80
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#define R 0x7F
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// Max number of bytes the LORA Rx/Tx FIFO can hold
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#define RH_RF95_FIFO_SIZE 255
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// This is the maximum number of bytes that can be carried by the LORA.
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// We use some for headers, keeping fewer for RadioHead messages
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#define RH_RF95_MAX_PAYLOAD_LEN RH_RF95_FIFO_SIZE
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// The length of the headers we add.
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// The headers are inside the LORA's payload
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#define RH_RF95_HEADER_LEN 4
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// This is the maximum message length that can be supported by this driver.
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// Can be pre-defined to a smaller size (to save SRAM) prior to including this header
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// Here we allow for 1 byte message length, 4 bytes headers, user data and 2 bytes of FCS
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#ifndef RH_RF95_MAX_MESSAGE_LEN
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#define RH_RF95_MAX_MESSAGE_LEN (RH_RF95_MAX_PAYLOAD_LEN - RH_RF95_HEADER_LEN)
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#endif
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// The crystal oscillator frequency of the module
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#define RH_RF95_FXOSC 32000000.0
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// The Frequency Synthesizer step = RH_RF95_FXOSC / 2^^19
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#define RH_RF95_FSTEP (RH_RF95_FXOSC / 524288)
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// Register names (LoRa Mode, from table 85)
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#define RH_RF95_REG_00_FIFO 0x00
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#define RH_RF95_REG_01_OP_MODE 0x01
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#define RH_RF95_REG_02_RESERVED 0x02
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#define RH_RF95_REG_03_RESERVED 0x03
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#define RH_RF95_REG_04_RESERVED 0x04
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#define RH_RF95_REG_05_RESERVED 0x05
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#define RH_RF95_REG_06_FRF_MSB 0x06
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#define RH_RF95_REG_07_FRF_MID 0x07
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#define RH_RF95_REG_08_FRF_LSB 0x08
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#define RH_RF95_REG_09_PA_CONFIG 0x09
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#define RH_RF95_REG_0A_PA_RAMP 0x0a
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#define RH_RF95_REG_0B_OCP 0x0b
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#define RH_RF95_REG_0C_LNA 0x0c
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#define RH_RF95_REG_0D_FIFO_ADDR_PTR 0x0d
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#define RH_RF95_REG_0E_FIFO_TX_BASE_ADDR 0x0e
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#define RH_RF95_REG_0F_FIFO_RX_BASE_ADDR 0x0f
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#define RH_RF95_REG_10_FIFO_RX_CURRENT_ADDR 0x10
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#define RH_RF95_REG_11_IRQ_FLAGS_MASK 0x11
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#define RH_RF95_REG_12_IRQ_FLAGS 0x12
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#define RH_RF95_REG_13_RX_NB_BYTES 0x13
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#define RH_RF95_REG_14_RX_HEADER_CNT_VALUE_MSB 0x14
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#define RH_RF95_REG_15_RX_HEADER_CNT_VALUE_LSB 0x15
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#define RH_RF95_REG_16_RX_PACKET_CNT_VALUE_MSB 0x16
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#define RH_RF95_REG_17_RX_PACKET_CNT_VALUE_LSB 0x17
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#define RH_RF95_REG_18_MODEM_STAT 0x18
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#define RH_RF95_REG_19_PKT_SNR_VALUE 0x19
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#define RH_RF95_REG_1A_PKT_RSSI_VALUE 0x1a
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#define RH_RF95_REG_1B_RSSI_VALUE 0x1b
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#define RH_RF95_REG_1C_HOP_CHANNEL 0x1c
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#define RH_RF95_REG_1D_MODEM_CONFIG1 0x1d
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#define RH_RF95_REG_1E_MODEM_CONFIG2 0x1e
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#define RH_RF95_REG_1F_SYMB_TIMEOUT_LSB 0x1f
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#define RH_RF95_REG_20_PREAMBLE_MSB 0x20
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#define RH_RF95_REG_21_PREAMBLE_LSB 0x21
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#define RH_RF95_REG_22_PAYLOAD_LENGTH 0x22
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#define RH_RF95_REG_23_MAX_PAYLOAD_LENGTH 0x23
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#define RH_RF95_REG_24_HOP_PERIOD 0x24
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#define RH_RF95_REG_25_FIFO_RX_BYTE_ADDR 0x25
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#define RH_RF95_REG_26_MODEM_CONFIG3 0x26
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#define RH_RF95_REG_40_DIO_MAPPING1 0x40
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#define RH_RF95_REG_41_DIO_MAPPING2 0x41
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#define RH_RF95_REG_42_VERSION 0x42
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#define RH_RF95_REG_4B_TCXO 0x4b
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#define RH_RF95_REG_4D_PA_DAC 0x4d
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#define RH_RF95_REG_5B_FORMER_TEMP 0x5b
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#define RH_RF95_REG_61_AGC_REF 0x61
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#define RH_RF95_REG_62_AGC_THRESH1 0x62
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#define RH_RF95_REG_63_AGC_THRESH2 0x63
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#define RH_RF95_REG_64_AGC_THRESH3 0x64
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// RH_RF95_REG_01_OP_MODE 0x01
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#define RH_RF95_LONG_RANGE_MODE 0x80
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#define RH_RF95_ACCESS_SHARED_REG 0x40
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#define RH_RF95_MODE 0x07
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#define RH_RF95_MODE_SLEEP 0x00
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#define RH_RF95_MODE_STDBY 0x01
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#define RH_RF95_MODE_FSTX 0x02
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#define RH_RF95_MODE_TX 0x03
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#define RH_RF95_MODE_FSRX 0x04
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#define RH_RF95_MODE_RXCONTINUOUS 0x05
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#define RH_RF95_MODE_RXSINGLE 0x06
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#define RH_RF95_MODE_CAD 0x07
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// RH_RF95_REG_09_PA_CONFIG 0x09
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#define RH_RF95_PA_SELECT 0x80
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#define RH_RF95_MAX_POWER 0x70
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#define RH_RF95_OUTPUT_POWER 0x0f
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// RH_RF95_REG_0A_PA_RAMP 0x0a
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#define RH_RF95_LOW_PN_TX_PLL_OFF 0x10
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#define RH_RF95_PA_RAMP 0x0f
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#define RH_RF95_PA_RAMP_3_4MS 0x00
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#define RH_RF95_PA_RAMP_2MS 0x01
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#define RH_RF95_PA_RAMP_1MS 0x02
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#define RH_RF95_PA_RAMP_500US 0x03
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#define RH_RF95_PA_RAMP_250US 0x0
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#define RH_RF95_PA_RAMP_125US 0x05
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#define RH_RF95_PA_RAMP_100US 0x06
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#define RH_RF95_PA_RAMP_62US 0x07
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#define RH_RF95_PA_RAMP_50US 0x08
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#define RH_RF95_PA_RAMP_40US 0x09
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#define RH_RF95_PA_RAMP_31US 0x0a
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#define RH_RF95_PA_RAMP_25US 0x0b
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#define RH_RF95_PA_RAMP_20US 0x0c
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#define RH_RF95_PA_RAMP_15US 0x0d
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#define RH_RF95_PA_RAMP_12US 0x0e
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#define RH_RF95_PA_RAMP_10US 0x0f
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// RH_RF95_REG_0B_OCP 0x0b
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#define RH_RF95_OCP_ON 0x20
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#define RH_RF95_OCP_TRIM 0x1f
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// RH_RF95_REG_0C_LNA 0x0c
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#define RH_RF95_LNA_GAIN 0xe0
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#define RH_RF95_LNA_BOOST 0x03
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#define RH_RF95_LNA_BOOST_DEFAULT 0x00
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#define RH_RF95_LNA_BOOST_150PC 0x11
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// RH_RF95_REG_11_IRQ_FLAGS_MASK 0x11
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#define RH_RF95_RX_TIMEOUT_MASK 0x80
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#define RH_RF95_RX_DONE_MASK 0x40
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#define RH_RF95_PAYLOAD_CRC_ERROR_MASK 0x20
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#define RH_RF95_VALID_HEADER_MASK 0x10
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#define RH_RF95_TX_DONE_MASK 0x08
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#define RH_RF95_CAD_DONE_MASK 0x04
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#define RH_RF95_FHSS_CHANGE_CHANNEL_MASK 0x02
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#define RH_RF95_CAD_DETECTED_MASK 0x01
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// RH_RF95_REG_12_IRQ_FLAGS 0x12
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#define RH_RF95_RX_TIMEOUT 0x80
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#define RH_RF95_RX_DONE 0x40
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#define RH_RF95_PAYLOAD_CRC_ERROR 0x20
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#define RH_RF95_VALID_HEADER 0x10
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#define RH_RF95_TX_DONE 0x08
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#define RH_RF95_CAD_DONE 0x04
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#define RH_RF95_FHSS_CHANGE_CHANNEL 0x02
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#define RH_RF95_CAD_DETECTED 0x01
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// RH_RF95_REG_18_MODEM_STAT 0x18
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#define RH_RF95_RX_CODING_RATE 0xe0
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#define RH_RF95_MODEM_STATUS_CLEAR 0x10
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#define RH_RF95_MODEM_STATUS_HEADER_INFO_VALID 0x08
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#define RH_RF95_MODEM_STATUS_RX_ONGOING 0x04
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#define RH_RF95_MODEM_STATUS_SIGNAL_SYNCHRONIZED 0x02
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#define RH_RF95_MODEM_STATUS_SIGNAL_DETECTED 0x01
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// RH_RF95_REG_1C_HOP_CHANNEL 0x1c
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#define RH_RF95_PLL_TIMEOUT 0x80
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#define RH_RF95_RX_PAYLOAD_CRC_IS_ON 0x40
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#define RH_RF95_FHSS_PRESENT_CHANNEL 0x3f
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// RH_RF95_REG_1D_MODEM_CONFIG1 0x1d
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#define RH_RF95_BW 0xc0
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#define RH_RF95_BW_125KHZ 0x00
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#define RH_RF95_BW_250KHZ 0x40
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#define RH_RF95_BW_500KHZ 0x80
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#define RH_RF95_BW_RESERVED 0xc0
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#define RH_RF95_CODING_RATE 0x38
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#define RH_RF95_CODING_RATE_4_5 0x00
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#define RH_RF95_CODING_RATE_4_6 0x08
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#define RH_RF95_CODING_RATE_4_7 0x10
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#define RH_RF95_CODING_RATE_4_8 0x18
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#define RH_RF95_IMPLICIT_HEADER_MODE_ON 0x04
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#define RH_RF95_RX_PAYLOAD_CRC_ON 0x02
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#define RH_RF95_LOW_DATA_RATE_OPTIMIZE 0x01
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// RH_RF95_REG_1E_MODEM_CONFIG2 0x1e
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#define RH_RF95_SPREADING_FACTOR 0xf0
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#define RH_RF95_SPREADING_FACTOR_64CPS 0x60
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#define RH_RF95_SPREADING_FACTOR_128CPS 0x70
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#define RH_RF95_SPREADING_FACTOR_256CPS 0x80
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#define RH_RF95_SPREADING_FACTOR_512CPS 0x90
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#define RH_RF95_SPREADING_FACTOR_1024CPS 0xa0
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#define RH_RF95_SPREADING_FACTOR_2048CPS 0xb0
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#define RH_RF95_SPREADING_FACTOR_4096CPS 0xc0
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#define RH_RF95_TX_CONTINUOUS_MOE 0x08
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#define RH_RF95_AGC_AUTO_ON 0x04
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#define RH_RF95_SYM_TIMEOUT_MSB 0x03
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// RH_RF95_REG_4D_PA_DAC 0x4d
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#define RH_RF95_PA_DAC_DISABLE 0x04
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#define RH_RF95_PA_DAC_ENABLE 0x07
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#define No_header 0
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#define Header_used 1
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#define Header No_header
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//CRC Types
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#define CRC_TYPE_CCITT 0
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#define CRC_TYPE_IBM 1
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//Polynomial = X^16 + X^12 + X^5 + 1
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#define POLYNOMIAL_CCITT 0x1021
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//Polynomial = X^16 + X^15 + X^2 + 1
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#define POLYNOMIAL_IBM 0x8005
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//Seeds
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#define CRC_IBM_SEED 0xFFFF
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#define CRC_CCITT_SEED 0x1D0F
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typedef enum
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{
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Bw125Cr45Sf128 = 0, ///< Bw = 125 kHz, Cr = 4/5, Sf = 128chips/symbol, CRC on. Default medium range
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Bw500Cr45Sf128, ///< Bw = 500 kHz, Cr = 4/5, Sf = 128chips/symbol, CRC on. Fast+short range
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Bw31_25Cr48Sf512, ///< Bw = 31.25 kHz, Cr = 4/8, Sf = 512chips/symbol, CRC on. Slow+long range
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Bw125Cr48Sf4096, ///< Bw = 125 kHz, Cr = 4/8, Sf = 4096chips/symbol, CRC on. Slow+long range
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IH_Bw125Cr45Sf128, ///< Bw = 125 kHz, Cr = 4/5, Sf = 128chips/symbol, CRC on. Default medium range + Implicit Header
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} ModemConfigChoice;
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typedef enum
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{
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RHModeInitialising = 0, ///< Transport is initialising. Initial default value until init() is called..
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RHModeSleep, ///< Transport hardware is in low power sleep mode (if supported)
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RHModeIdle, ///< Transport is idle.
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RHModeTx, ///< Transport is in the process of transmitting a message.
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RHModeRx, ///< Transport is in the process of receiving a message.
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RHModeCad,
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} RHMode;
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HAL_StatusTypeDef RF95_write(char reg, char wValue);
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HAL_StatusTypeDef RF95_write_burst(char reg, uint8_t* data);
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char RF95_read(char reg);
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HAL_StatusTypeDef RF95_read_burst(char reg, char* buffer, int length);
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//=====Init and configuration=====//
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bool RF95_Init(void);
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void RF95_Reset(void);
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bool RF95_setModemConfig(ModemConfigChoice index);
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void RF95_setPreambleLength(uint16_t bytes);
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void RF95_setTxPower(int8_t power, bool useRFO);
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bool RF95_setFrequency(float centre);
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//=====Send and receive=====//
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bool RF95_receive(uint8_t* buf);
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bool RF95_receive_Timeout(uint8_t* buf, uint16_t timeout);
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bool RF95_send(uint8_t* data);
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//=====Control=====//
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bool RF95_available(void);
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bool RF95_available_Timeout(uint16_t timeout);
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bool RF95_available_Timeout(uint16_t timeout);
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bool RF95_waitPacketSent(void);
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bool RF95_waitCAD(void);
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//=====Modes Configuration=====//
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void RF95_setModeIdle(void);
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bool RF95_sleep(void);
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void RF95_setModeRx_Continuous(void);
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void RF95_setModeRx_Single(void);
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void RF95_setModeTx(void);
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void RF95_setModeCAD(void);
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//=====Check flags=====//
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bool RF95_Check_RxTimeout(void);
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bool RF95_Check_RxDone(void);
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bool RF95_Check_PayloadCRCError(void);
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bool RF95_Check_ValidHeader(void);
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bool RF95_Check_TxDone(void);
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bool RF95_Check_CADDone(void);
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bool RF95_Check_FhssChannelChange(void);
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bool RF95_Check_CADDetect(void);
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void RF95_Clear_IRQ(void);
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bool RF95_Check_ModemClear(void);
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bool RF95_Check_HeaderInfoValid(void);
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bool RF95_Check_RxOnGoing(void);
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bool RF95_Check_SignalSyncronized(void);
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bool RF95_Check_SignalDetect(void);
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//=====CRC calculation=====//
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uint16_t ComputeCRC(uint16_t crc, uint8_t data, uint16_t polynomial);
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uint16_t RF95_ComputeCRC(uint8_t *buffer, uint8_t bufferLength, uint8_t crcType);
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//========================================================================
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//=======================Communication protocol===========================
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//========================================================================
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/* The communication protocol uses three kinds of symbols
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* + '?' -> to make petitions to a certain node
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* + 'O' -> to say something has been done correctly or to continue
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* + 'X' -> to say something has gone wrong or to stop
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* All of them are followed with the name of the node, which is only a number.
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*/
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#define Num_of_Nodes 2
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#define Node_ID 1
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void Clear_Buffer(uint8_t* buffer);
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bool RF95_Master_Receive_from_Node(uint16_t node);
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bool RF95_Master_Receive_from_All_Nodes(void);
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bool RF95_Slave_Send(void);
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#endif
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