/*============================================================================================================== * To use this library a buffer called LoRa_buff has been created * and we'll have to configure the parameters for LoRa in the RF95_Init() 1. include the declaration "extern uint8_t LoRa_buff[RH_RF95_FIFO_SIZE];" in the main.c. 2. Follow these steps for the sending/reception of data: -----------Send Mode------------- RF95_Init(); strcpy(LoRa_buff, "Test to send"); //It is necessary to use the buffer LoRa_buff and the function strcpy to //copy the data to the buffer, if not the program will send nothing. RF95_send(LoRa_buff); ---------------------------------- -----------Reception Mode------------- RF95_Init(); RF95_setModeRx_Continuous(); RF95_receive(LoRa_buff); ---------------------------------- ==============================================================================================================*/ #ifndef _LORA_RF95_ #define _LORA_RF95_ //#include "main.h" #include "spi.hpp" //#include "stm32l4xx_hal_def.h" #include #include #include #include //#include "Useful_Functions.h" //Modifiers for read and send #define W 0x80 #define R 0x7F // Max number of bytes the LORA Rx/Tx FIFO can hold #define RH_RF95_FIFO_SIZE 255 // This is the maximum number of bytes that can be carried by the LORA. // We use some for headers, keeping fewer for RadioHead messages #define RH_RF95_MAX_PAYLOAD_LEN RH_RF95_FIFO_SIZE // The length of the headers we add. // The headers are inside the LORA's payload #define RH_RF95_HEADER_LEN 4 // This is the maximum message length that can be supported by this driver. // Can be pre-defined to a smaller size (to save SRAM) prior to including this header // Here we allow for 1 byte message length, 4 bytes headers, user data and 2 bytes of FCS #ifndef RH_RF95_MAX_MESSAGE_LEN #define RH_RF95_MAX_MESSAGE_LEN (RH_RF95_MAX_PAYLOAD_LEN - RH_RF95_HEADER_LEN) #endif // The crystal oscillator frequency of the module #define RH_RF95_FXOSC 32000000.0 // The Frequency Synthesizer step = RH_RF95_FXOSC / 2^^19 #define RH_RF95_FSTEP (RH_RF95_FXOSC / 524288) // Register names (LoRa Mode, from table 85) #define RH_RF95_REG_00_FIFO 0x00 #define RH_RF95_REG_01_OP_MODE 0x01 #define RH_RF95_REG_02_RESERVED 0x02 #define RH_RF95_REG_03_RESERVED 0x03 #define RH_RF95_REG_04_RESERVED 0x04 #define RH_RF95_REG_05_RESERVED 0x05 #define RH_RF95_REG_06_FRF_MSB 0x06 #define RH_RF95_REG_07_FRF_MID 0x07 #define RH_RF95_REG_08_FRF_LSB 0x08 #define RH_RF95_REG_09_PA_CONFIG 0x09 #define RH_RF95_REG_0A_PA_RAMP 0x0a #define RH_RF95_REG_0B_OCP 0x0b #define RH_RF95_REG_0C_LNA 0x0c #define RH_RF95_REG_0D_FIFO_ADDR_PTR 0x0d #define RH_RF95_REG_0E_FIFO_TX_BASE_ADDR 0x0e #define RH_RF95_REG_0F_FIFO_RX_BASE_ADDR 0x0f #define RH_RF95_REG_10_FIFO_RX_CURRENT_ADDR 0x10 #define RH_RF95_REG_11_IRQ_FLAGS_MASK 0x11 #define RH_RF95_REG_12_IRQ_FLAGS 0x12 #define RH_RF95_REG_13_RX_NB_BYTES 0x13 #define RH_RF95_REG_14_RX_HEADER_CNT_VALUE_MSB 0x14 #define RH_RF95_REG_15_RX_HEADER_CNT_VALUE_LSB 0x15 #define RH_RF95_REG_16_RX_PACKET_CNT_VALUE_MSB 0x16 #define RH_RF95_REG_17_RX_PACKET_CNT_VALUE_LSB 0x17 #define RH_RF95_REG_18_MODEM_STAT 0x18 #define RH_RF95_REG_19_PKT_SNR_VALUE 0x19 #define RH_RF95_REG_1A_PKT_RSSI_VALUE 0x1a #define RH_RF95_REG_1B_RSSI_VALUE 0x1b #define RH_RF95_REG_1C_HOP_CHANNEL 0x1c #define RH_RF95_REG_1D_MODEM_CONFIG1 0x1d #define RH_RF95_REG_1E_MODEM_CONFIG2 0x1e #define RH_RF95_REG_1F_SYMB_TIMEOUT_LSB 0x1f #define RH_RF95_REG_20_PREAMBLE_MSB 0x20 #define RH_RF95_REG_21_PREAMBLE_LSB 0x21 #define RH_RF95_REG_22_PAYLOAD_LENGTH 0x22 #define RH_RF95_REG_23_MAX_PAYLOAD_LENGTH 0x23 #define RH_RF95_REG_24_HOP_PERIOD 0x24 #define RH_RF95_REG_25_FIFO_RX_BYTE_ADDR 0x25 #define RH_RF95_REG_26_MODEM_CONFIG3 0x26 #define RH_RF95_REG_40_DIO_MAPPING1 0x40 #define RH_RF95_REG_41_DIO_MAPPING2 0x41 #define RH_RF95_REG_42_VERSION 0x42 #define RH_RF95_REG_4B_TCXO 0x4b #define RH_RF95_REG_4D_PA_DAC 0x4d #define RH_RF95_REG_5B_FORMER_TEMP 0x5b #define RH_RF95_REG_61_AGC_REF 0x61 #define RH_RF95_REG_62_AGC_THRESH1 0x62 #define RH_RF95_REG_63_AGC_THRESH2 0x63 #define RH_RF95_REG_64_AGC_THRESH3 0x64 // RH_RF95_REG_01_OP_MODE 0x01 #define RH_RF95_LONG_RANGE_MODE 0x80 #define RH_RF95_ACCESS_SHARED_REG 0x40 #define RH_RF95_MODE 0x07 #define RH_RF95_MODE_SLEEP 0x00 #define RH_RF95_MODE_STDBY 0x01 #define RH_RF95_MODE_FSTX 0x02 #define RH_RF95_MODE_TX 0x03 #define RH_RF95_MODE_FSRX 0x04 #define RH_RF95_MODE_RXCONTINUOUS 0x05 #define RH_RF95_MODE_RXSINGLE 0x06 #define RH_RF95_MODE_CAD 0x07 // RH_RF95_REG_09_PA_CONFIG 0x09 #define RH_RF95_PA_SELECT 0x80 #define RH_RF95_MAX_POWER 0x70 #define RH_RF95_OUTPUT_POWER 0x0f // RH_RF95_REG_0A_PA_RAMP 0x0a #define RH_RF95_LOW_PN_TX_PLL_OFF 0x10 #define RH_RF95_PA_RAMP 0x0f #define RH_RF95_PA_RAMP_3_4MS 0x00 #define RH_RF95_PA_RAMP_2MS 0x01 #define RH_RF95_PA_RAMP_1MS 0x02 #define RH_RF95_PA_RAMP_500US 0x03 #define RH_RF95_PA_RAMP_250US 0x0 #define RH_RF95_PA_RAMP_125US 0x05 #define RH_RF95_PA_RAMP_100US 0x06 #define RH_RF95_PA_RAMP_62US 0x07 #define RH_RF95_PA_RAMP_50US 0x08 #define RH_RF95_PA_RAMP_40US 0x09 #define RH_RF95_PA_RAMP_31US 0x0a #define RH_RF95_PA_RAMP_25US 0x0b #define RH_RF95_PA_RAMP_20US 0x0c #define RH_RF95_PA_RAMP_15US 0x0d #define RH_RF95_PA_RAMP_12US 0x0e #define RH_RF95_PA_RAMP_10US 0x0f // RH_RF95_REG_0B_OCP 0x0b #define RH_RF95_OCP_ON 0x20 #define RH_RF95_OCP_TRIM 0x1f // RH_RF95_REG_0C_LNA 0x0c #define RH_RF95_LNA_GAIN 0xe0 #define RH_RF95_LNA_BOOST 0x03 #define RH_RF95_LNA_BOOST_DEFAULT 0x00 #define RH_RF95_LNA_BOOST_150PC 0x11 // RH_RF95_REG_11_IRQ_FLAGS_MASK 0x11 #define RH_RF95_RX_TIMEOUT_MASK 0x80 #define RH_RF95_RX_DONE_MASK 0x40 #define RH_RF95_PAYLOAD_CRC_ERROR_MASK 0x20 #define RH_RF95_VALID_HEADER_MASK 0x10 #define RH_RF95_TX_DONE_MASK 0x08 #define RH_RF95_CAD_DONE_MASK 0x04 #define RH_RF95_FHSS_CHANGE_CHANNEL_MASK 0x02 #define RH_RF95_CAD_DETECTED_MASK 0x01 // RH_RF95_REG_12_IRQ_FLAGS 0x12 #define RH_RF95_RX_TIMEOUT 0x80 #define RH_RF95_RX_DONE 0x40 #define RH_RF95_PAYLOAD_CRC_ERROR 0x20 #define RH_RF95_VALID_HEADER 0x10 #define RH_RF95_TX_DONE 0x08 #define RH_RF95_CAD_DONE 0x04 #define RH_RF95_FHSS_CHANGE_CHANNEL 0x02 #define RH_RF95_CAD_DETECTED 0x01 // RH_RF95_REG_18_MODEM_STAT 0x18 #define RH_RF95_RX_CODING_RATE 0xe0 #define RH_RF95_MODEM_STATUS_CLEAR 0x10 #define RH_RF95_MODEM_STATUS_HEADER_INFO_VALID 0x08 #define RH_RF95_MODEM_STATUS_RX_ONGOING 0x04 #define RH_RF95_MODEM_STATUS_SIGNAL_SYNCHRONIZED 0x02 #define RH_RF95_MODEM_STATUS_SIGNAL_DETECTED 0x01 // RH_RF95_REG_1C_HOP_CHANNEL 0x1c #define RH_RF95_PLL_TIMEOUT 0x80 #define RH_RF95_RX_PAYLOAD_CRC_IS_ON 0x40 #define RH_RF95_FHSS_PRESENT_CHANNEL 0x3f // RH_RF95_REG_1D_MODEM_CONFIG1 0x1d #define RH_RF95_BW 0xc0 #define RH_RF95_BW_125KHZ 0x00 #define RH_RF95_BW_250KHZ 0x40 #define RH_RF95_BW_500KHZ 0x80 #define RH_RF95_BW_RESERVED 0xc0 #define RH_RF95_CODING_RATE 0x38 #define RH_RF95_CODING_RATE_4_5 0x00 #define RH_RF95_CODING_RATE_4_6 0x08 #define RH_RF95_CODING_RATE_4_7 0x10 #define RH_RF95_CODING_RATE_4_8 0x18 #define RH_RF95_IMPLICIT_HEADER_MODE_ON 0x04 #define RH_RF95_RX_PAYLOAD_CRC_ON 0x02 #define RH_RF95_LOW_DATA_RATE_OPTIMIZE 0x01 // RH_RF95_REG_1E_MODEM_CONFIG2 0x1e #define RH_RF95_SPREADING_FACTOR 0xf0 #define RH_RF95_SPREADING_FACTOR_64CPS 0x60 #define RH_RF95_SPREADING_FACTOR_128CPS 0x70 #define RH_RF95_SPREADING_FACTOR_256CPS 0x80 #define RH_RF95_SPREADING_FACTOR_512CPS 0x90 #define RH_RF95_SPREADING_FACTOR_1024CPS 0xa0 #define RH_RF95_SPREADING_FACTOR_2048CPS 0xb0 #define RH_RF95_SPREADING_FACTOR_4096CPS 0xc0 #define RH_RF95_TX_CONTINUOUS_MOE 0x08 #define RH_RF95_AGC_AUTO_ON 0x04 #define RH_RF95_SYM_TIMEOUT_MSB 0x03 // RH_RF95_REG_4D_PA_DAC 0x4d #define RH_RF95_PA_DAC_DISABLE 0x04 #define RH_RF95_PA_DAC_ENABLE 0x07 #define No_header 0 #define Header_used 1 #define Header No_header //CRC Types #define CRC_TYPE_CCITT 0 #define CRC_TYPE_IBM 1 //Polynomial = X^16 + X^12 + X^5 + 1 #define POLYNOMIAL_CCITT 0x1021 //Polynomial = X^16 + X^15 + X^2 + 1 #define POLYNOMIAL_IBM 0x8005 //Seeds #define CRC_IBM_SEED 0xFFFF #define CRC_CCITT_SEED 0x1D0F typedef enum { Bw125Cr45Sf128 = 0, ///< Bw = 125 kHz, Cr = 4/5, Sf = 128chips/symbol, CRC on. Default medium range Bw500Cr45Sf128, ///< Bw = 500 kHz, Cr = 4/5, Sf = 128chips/symbol, CRC on. Fast+short range Bw31_25Cr48Sf512, ///< Bw = 31.25 kHz, Cr = 4/8, Sf = 512chips/symbol, CRC on. Slow+long range Bw125Cr48Sf4096, ///< Bw = 125 kHz, Cr = 4/8, Sf = 4096chips/symbol, CRC on. Slow+long range IH_Bw125Cr45Sf128, ///< Bw = 125 kHz, Cr = 4/5, Sf = 128chips/symbol, CRC on. Default medium range + Implicit Header } ModemConfigChoice; typedef enum { RHModeInitialising = 0, ///< Transport is initialising. Initial default value until init() is called.. RHModeSleep, ///< Transport hardware is in low power sleep mode (if supported) RHModeIdle, ///< Transport is idle. RHModeTx, ///< Transport is in the process of transmitting a message. RHModeRx, ///< Transport is in the process of receiving a message. RHModeCad, } RHMode; HAL_StatusTypeDef RF95_write(char reg, char wValue); HAL_StatusTypeDef RF95_write_burst(char reg, uint8_t* data); char RF95_read(char reg); HAL_StatusTypeDef RF95_read_burst(char reg, char* buffer, int length); //=====Init and configuration=====// bool RF95_Init(void); void RF95_Reset(void); bool RF95_setModemConfig(ModemConfigChoice index); void RF95_setPreambleLength(uint16_t bytes); void RF95_setTxPower(int8_t power, bool useRFO); bool RF95_setFrequency(float centre); //=====Send and receive=====// bool RF95_receive(uint8_t* buf); bool RF95_receive_Timeout(uint8_t* buf, uint16_t timeout); bool RF95_send(uint8_t* data); //=====Control=====// bool RF95_available(void); bool RF95_available_Timeout(uint16_t timeout); bool RF95_available_Timeout(uint16_t timeout); bool RF95_waitPacketSent(void); bool RF95_waitCAD(void); //=====Modes Configuration=====// void RF95_setModeIdle(void); bool RF95_sleep(void); void RF95_setModeRx_Continuous(void); void RF95_setModeRx_Single(void); void RF95_setModeTx(void); void RF95_setModeCAD(void); //=====Check flags=====// bool RF95_Check_RxTimeout(void); bool RF95_Check_RxDone(void); bool RF95_Check_PayloadCRCError(void); bool RF95_Check_ValidHeader(void); bool RF95_Check_TxDone(void); bool RF95_Check_CADDone(void); bool RF95_Check_FhssChannelChange(void); bool RF95_Check_CADDetect(void); void RF95_Clear_IRQ(void); bool RF95_Check_ModemClear(void); bool RF95_Check_HeaderInfoValid(void); bool RF95_Check_RxOnGoing(void); bool RF95_Check_SignalSyncronized(void); bool RF95_Check_SignalDetect(void); //=====CRC calculation=====// uint16_t ComputeCRC(uint16_t crc, uint8_t data, uint16_t polynomial); uint16_t RF95_ComputeCRC(uint8_t *buffer, uint8_t bufferLength, uint8_t crcType); //======================================================================== //=======================Communication protocol=========================== //======================================================================== /* The communication protocol uses three kinds of symbols * + '?' -> to make petitions to a certain node * + 'O' -> to say something has been done correctly or to continue * + 'X' -> to say something has gone wrong or to stop * All of them are followed with the name of the node, which is only a number. */ #define Num_of_Nodes 2 #define Node_ID 1 void Clear_Buffer(uint8_t* buffer); bool RF95_Master_Receive_from_Node(uint16_t node); bool RF95_Master_Receive_from_All_Nodes(void); bool RF95_Slave_Send(void); #endif